1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to a flash electrically erasabIe programmable read-only memory (EEPROM).
2. Description of the Related Art
In a nonvolatile memory device, an electrical write operation can be carried out after the device is mounted on a printed board. One typical example of such a device is a flash memory which bas an advantage in that data storage is possible without a backup battery and which is highly integrated. However, the flash memory is disadvantageous in terms of time of taken for erasing/writing operations, necessity of two power supplies such as 5 V and 12 V, and impossibility of reducing the voltages of the power supplies.
Generally, a flash memory is completely erased in one operation. However, in order to be compatible with a hard disk device (HDD) or a floppy disk device (FDD), there have been suggested two kinds of sector erasable technology: a method of applying a positive voltage to sources; and a method of applying a negative voltage to control gates.
For example, a NOR type flash EEPROM is formed by a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells each connected to one of the word lines and one of the bit lines. In this case, one of the nonvolatile memory cells has a source, a drain connected to one of the bit lines, a floating gate, and a control gate connected to one of the word lines.
According to the method of applying a positive voltage, a plurality of sources of the memory cells are divided into a plurality of sectors. For example, in order to suppress an increase in chip area of the flash EEPROM, each sector is made long along the bit lines, In this case, all the memory cells connected to the same bit line are simultaneously erased by applying a positive voltage to the sources thereof utilizing Fowler-Nordheim tunneling, and thereafter, a writing operation is performed upon each of the memory cells. Therefore, each of the memory cells receives a drain disturbance by the write operation upon the other memory cells; however, the maximum number of drain disturbances is n-1, where n is the number of memory cells connected to one bit line, since drain disturbances before each writing operation upon the memory cells are never accumulated. Also, when erasing/writing operations are performed upon one selector, no stress is imposed on the memory cells of the other sectors, i.e., no drain disturbance is caused in the memory cells of the other sectors
However, if the number of sectors is increased by adopting the above-mentioned positive voltage-applying method, the chip area of the flash EEPROM is remarkably increased due to the increased number of con, non source regions of the memory cells.
On the one hand, according to the negative voltage-applying method, a negative voltage is applied to one word line, i.e,, the control gates of the memory cells connected thereto. In this case, a positive voltage is applied to all the sources or the substrate. Thus, electrons of the floating gates of the memory cells connected to the same word line are expelled to the source or the substrate due to Fowler-Nordheim tunneling, to thereby erase the memory cells (see: Hitoshi Kume et al., "A 3.42 .mu.m.sup.2 Flash Memory Cell Technology Conformable to a Sector Erase", Symp. VLSI Tech, 1991, pp. 77-78). That is, one sector is formed by the memory cells connected to one word line (or two or more word lines). In this case, it is unnecessary to divide the source regions of the memory cells into a plurality of sectors, and accordingly, the chip area of the flash EEPROM is not increased. However, when erasing/writing operations are performed upon one selector (one word line), a drain disturbance is always caused in the memory cells of the other sectors (the other word lines). In addition, since an erasing operation is never performed upon a memory cell unless a sector including this memory cell is selected, drain disturbances may be accumulated within the memory cells of the non-selected sectors. That is, according to the negative voltage-applying method, since the tolerance to accumulated drain disturbances is so small as compared with the positive voltage-applying method, the device must be designed for enduring this tolerance.
Note that, it has been suggested that the concentration of impurities in the drains of memory cells be reduced, to thereby enhance the tolerance to accumulated drain disturbances (also see the above-mentioned document). In this case, however, if the concentration of impurities in the drains is fluctuated, the tolerance of drain disturbances may be remarkably deteriorated. Also, if the concentration of impurities in sources is the same as that of impurities in drains, the erasing speed for electrons to expel to the sources is reduced. Otherwise, i.e., if the concentration of impurities in the sources is different from that of impurities in the drains, the manufacturing steps are increased, thus increasing the manufacturing cost.